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A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Feb2021, Vol. 68 Issue 2, p603-616. 14p. - Publication Year :
- 2021
-
Abstract
- In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional- ${N}$ multiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48ps root-mean-square (RMS) jitter in fractional- ${N}$ and integer- ${N}$ modes, respectively. The fractional spur is less than −59.0dBc, and the reference spur is −64.5dBc. The power consumptions are 1.85mW and 1.22mW, corresponding to figures of merit (FOM) of −240.4dB and −245.5dB. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 68
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 148207849
- Full Text :
- https://doi.org/10.1109/TCSI.2020.3035373