Cite
Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/IDS Methodology.
MLA
Tajalli, Armin. “Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/IDS Methodology.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 68, no. 2, Feb. 2021, pp. 631–40. EBSCOhost, https://doi.org/10.1109/TCSI.2020.3036683.
APA
Tajalli, A. (2021). Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/IDS Methodology. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 68(2), 631–640. https://doi.org/10.1109/TCSI.2020.3036683
Chicago
Tajalli, Armin. 2021. “Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/IDS Methodology.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 68 (2): 631–40. doi:10.1109/TCSI.2020.3036683.