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A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Feb2021, Vol. 68 Issue 2, p557-568. 12p. - Publication Year :
- 2021
-
Abstract
- This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rd Nyquist zone. The converter’s front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers’ inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC’s power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step. [ABSTRACT FROM AUTHOR]
- Subjects :
- *ANALOG-to-digital converters
*ELECTRIC power filters
*CALIBRATION
*ODDS ratio
Subjects
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 68
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 148207873
- Full Text :
- https://doi.org/10.1109/TCSI.2020.3039252