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Synthesis of Lithography Test Patterns Using Machine Learning Model.
- Source :
-
IEEE Transactions on Semiconductor Manufacturing . Feb2021, Vol. 34 Issue 1, p49-57. 9p. - Publication Year :
- 2021
-
Abstract
- Diversity of test patterns is important for many lithography applications. It is however difficult to achieve with sample layouts or by using a popular pattern generator. We propose a synthesis method of lithography test patterns. Each pattern is represented by a map of IPS (image parameter space) values, called IPS map. A key in the proposed method is to guarantee that the center of the synthesized pattern corresponds to the IPS values given as input. The synthesis consists of three steps: a new IPS map is generated using an adversarial auto-encoder (AAE) with given IPS values; the IPS map is converted to its corresponding layout through an auto-encoder (AE); the layout goes through the final processing to remove any unrealistic shapes. Both AAE and AE are trained beforehand by using a few sample layouts. The synthesis method is applied to lithography modeling. The RMSE of lithography model is reduced by 30% when the model is calibrated with synthesized patterns, compared to the model based on test patterns from a pattern generator. A machine learning-based lithography simulation is taken as a second application. When the synthesized patterns are used to train the machine learning model, the accuracy of lithography simulation improves by 7%. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 08946507
- Volume :
- 34
- Issue :
- 1
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Semiconductor Manufacturing
- Publication Type :
- Academic Journal
- Accession number :
- 148595874
- Full Text :
- https://doi.org/10.1109/TSM.2021.3052302