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A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . May2021, Vol. 68 Issue 5, p1881-1891. 11p. - Publication Year :
- 2021
-
Abstract
- In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL’s phase detector (2.7–4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of −232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of −247dB, and normalized TR and area (FOMTA) of −262dB. [ABSTRACT FROM AUTHOR]
- Subjects :
- *PHASE-locked loops
*CAPACITOR switching
*PHASE detectors
*TIME-digital conversion
Subjects
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 68
- Issue :
- 5
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 149962507
- Full Text :
- https://doi.org/10.1109/TCSI.2021.3059484