Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach.

The retention flip-flop is an essential component in power gated circuits for retaining state during the sleep mode. In this article, we solve two critical limitations of the conventional approaches to the allocation of state retention storage for power gated circuits. Those are: 1) the long wakeup delay caused by the senseless use of multibit retention flip-flops (MBRFFs) and 2) the inability to optimize retention flip-flops for the flip-flops with mux-feedback loop. It should be noted that the conventional approaches have regarded the long wakeup delay as an inevitable consequence of maximizing the reduction of total storage size for state retention while they have treated the flip-flops with mux-feedback loop (called self-loop flip-flop) as nonoptimizable component, but practically, the self-loop flip-flops synthesized from hardware description language (HDL) code are not far from a small amount and thus, can in no way be negligible. More precisely, for solving: 1), we show that the use of MBRFFs with up to 2 bits, consequently, constraining the wakeup delay to no more than two clock cycles, is enough to maintain the high reduction of total retention storage and for solving 2), we devise a 2-phase retention control mechanism for a pair of flip-flops, one of which has self-loop, by which just a single retention bit can be used to restore state of the two flip-flops. We propose an independent set-based algorithm for maximally extracting the nonconflict pairs from circuits. In addition, to further reduce the power consumption in the sleep mode, we propose a new design of 2-bit MBRFF. [ABSTRACT FROM AUTHOR]