Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories.

This article investigates the impact of interface trapped-charge variations on the dimensional scaling of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) under two scenarios: a uniform ferroelectric and random ferroelectric-dielectric (FE-DE) phase distribution. Our study indicates that both memory window (MW) and read margin decrease with increasing trap density (< nT >), and the MW of FeFET devices with scaled channel width can be more vulnerable to the trapped-charge variations than that with scaled gate length. Under the presence of the FE-DE phase variation, for low < nT >, the impact of trapped charges is mainly on the MW degradation for the high MW instances. As the < nT > continues to rise, the trapped charges can further worsen the worst case MW significantly. Besides, when down-scaling the interfacial layer thickness of the FeFET device to increase the MW, the increased σ MW due to the random interface trapped charges may also need to be considered. Our study may provide insights for device design with advanced FeFET NVMs. [ABSTRACT FROM AUTHOR]