Negative capacitance enables GAA scaling VDD to 0.5 V.

• Negative capacitance (NC) may enable gate-all-around FET scaling beyond 0.5 nm node. • 3-D Ginzburg-Landau-Khalatnikov model is adopted in the TCAD simulation. • The parameters of ferroelectric are extracted from an experimental C-V result. • The NC benefits are retained over a varying set of ferroelectric parameters. We present a TCAD simulation of the negative capacitance gate-all-around (NCGAA) field-effect transistor with the 3-D Ginzburg-Landau-Khalatnikov Model. The baseline device is based on the 2020 IRDS Table, and the mobility model is calibrated to account for ballistic transport and to match the "1.5 nm node" IRDS on-current requirement. The NC parameters are extracted from experimental C-V data. The NC-GAA shows reduction in the off current by one order of magnitude and a 40% on-current boost. If the gate work function is shifted to align the NC-GAA's off-current with the IRDS high performance requirement, it is shown that NC-GAA can achieve the on-current and V DD requirement of every node through the "0.7 eq node," which is the last node predicted in the 2020 IRDS Table. Furthermore, NC-GAA can even achieve a "0.5 eq node," which is three additional nodes beyond the baseline "1.5 nm node." We also show that these benefits are retained over a varying set of ferroelectric parameters. [ABSTRACT FROM AUTHOR]