Interface admittance measurement and simulation of dual gated CVD WS2 MOSCAPs: Mapping the DIT(E) profile.

• Dual gated WS 2 MOSCAP devices were fabricated to measure both n/p-branch C-V response. • Frequency/temperature dependent CV curves were correlated with WS 2 MOSCAP simulation. • Interface trap density across the bandgap (D IT (E)) is extracted for 2ML WS 2. Dual gated 2ML WS 2 MOS Capacitors have been fabricated with capacitance values as high as 2.7uF/cm2 (with single sheet charge centroid assumption for the WS 2 channel). Frequency and temperature dependent C-V measurements were correlated with simulations to extract the interface trap density-energy (D IT (E)) profile. We observe an exponentially decaying defect distribution from the conduction band (E C) edge with a magnitude of 8 × 1013 cm−2 eV−1 and an inverse slope of 0.12 eV and a similar distribution with a peak magnitude of 1.2 × 1014 cm−2 eV−1 from the valence band (E V) edge with an inverse slope of 0.12 eV. [ABSTRACT FROM AUTHOR]