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CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder.
- Source :
-
Circuits, Systems & Signal Processing . Aug2021, Vol. 40 Issue 8, p4089-4105. 17p. - Publication Year :
- 2021
-
Abstract
- This paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dual- V DD ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages ( V DD & V DD / 2 ) and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs. The performance of the proposed CNFET dual- V DD HA has been compared with the same circuit implemented with 45 nm MOSFETs and also with other CNFET-based state-of-the-art HA designs proposed in the literature. The proposed HA consumes merely 86 nW of power which is significantly lesser (66–90% lower) than the power required by other ternary HA designs, and also exhibits 69–91% lower delays. The overall PDP of the proposed HA circuit is merely 4–11% of the PDP of corresponding CMOS ternary HA and other benchmarked CNFET HA designs. [ABSTRACT FROM AUTHOR]
- Subjects :
- *CARBON nanotubes
*POWER resources
*CARBON paper
Subjects
Details
- Language :
- English
- ISSN :
- 0278081X
- Volume :
- 40
- Issue :
- 8
- Database :
- Academic Search Index
- Journal :
- Circuits, Systems & Signal Processing
- Publication Type :
- Academic Journal
- Accession number :
- 151385376
- Full Text :
- https://doi.org/10.1007/s00034-021-01664-2