Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme.

MLA

Sheikhpur, Saeideh, et al. “Strengthened 32‐bit AES Implementation: Architectural Error Correction Configuration with a New Voting Scheme.” IET Computers & Digital Techniques (Wiley-Blackwell), vol. 15, no. 6, Nov. 2021, pp. 395–408. EBSCOhost, https://doi.org/10.1049/cdt2.12031.

APA

Sheikhpur, S., Taheri, M., Ansari, M. S., & Mahani, A. (2021). Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme. IET Computers & Digital Techniques (Wiley-Blackwell), 15(6), 395–408. https://doi.org/10.1049/cdt2.12031

Chicago

Sheikhpur, Saeideh, Mahdi Taheri, Mohammad Saeed Ansari, and Ali Mahani. 2021. “Strengthened 32‐bit AES Implementation: Architectural Error Correction Configuration with a New Voting Scheme.” IET Computers & Digital Techniques (Wiley-Blackwell) 15 (6): 395–408. doi:10.1049/cdt2.12031.