A CMOS standard-cell based fully-synthesizable low-dropout regulator for ultra-low power applications.

This article presents a fully-synthesizable digital voltage regulator for applications with extremely low power consumption. The proposed design uses a synthesizable controller (DLDOC) to detect load fluctuations and control a tri-loop structural design. This tri-loop structure minimizes the ripples on output voltage (V OUT) and provides a fast-transient response (TR). This structure decreases the length of bi-directional shift register (Bi-SR) which reduces the overall power consumption. A quivering control is introduced to minimize the V OUT oscillations in steady-state. To demonstrate this design using CMOS standard-cells, a fully-synthesizable comparator (FS-comp) is utilized. A tri-state buffer array (TBA) is employed instead of conventional PMOS switch array to make this design fully-synthesizable. A pattern detection mechanism is used to switch between different loops. The proposed prototype occupies 6394 µm2 area in 45 nm CMOS technology. This design is implemented using conventional synthesis and place-and-route (P & R). For a supply voltage (VDD) of 0.5–1 V, a regulated V OUT is attained with a dropout voltage of 50 mV. At 10 MHz clock frequency, the proposed LDO achieves a quiescent current (I Q) and fast-TR of 2.2 µA and 300 ns, respectively. A maximum current efficiency (C.E.) of 99.98% is attained with output ripples < 1 mV. [ABSTRACT FROM AUTHOR]