Cite
Scalable Fully Pipelined Hardware Architecture for In-Network Aggregated AllReduce Communication.
MLA
Liu, Yao, et al. “Scalable Fully Pipelined Hardware Architecture for In-Network Aggregated AllReduce Communication.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 68, no. 10, Oct. 2021, pp. 4194–206. EBSCOhost, https://doi.org/10.1109/TCSI.2021.3098841.
APA
Liu, Y., Zhang, J., Liu, S., Wang, Q., Dai, W., & Cheung, R. C. C. (2021). Scalable Fully Pipelined Hardware Architecture for In-Network Aggregated AllReduce Communication. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 68(10), 4194–4206. https://doi.org/10.1109/TCSI.2021.3098841
Chicago
Liu, Yao, Junyi Zhang, Shuo Liu, Qiaoling Wang, Wangchen Dai, and Ray Chak Chung Cheung. 2021. “Scalable Fully Pipelined Hardware Architecture for In-Network Aggregated AllReduce Communication.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 68 (10): 4194–4206. doi:10.1109/TCSI.2021.3098841.