Cite
DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks.
MLA
Xie, Ruiqi, et al. “DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 68, no. 12, Dec. 2021, pp. 5095–107. EBSCOhost, https://doi.org/10.1109/TCSI.2021.3112826.
APA
Xie, R., Yin, J., & Han, J. (2021). DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 68(12), 5095–5107. https://doi.org/10.1109/TCSI.2021.3112826
Chicago
Xie, Ruiqi, Jun Yin, and Jun Han. 2021. “DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 68 (12): 5095–5107. doi:10.1109/TCSI.2021.3112826.