Cite
Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs.
MLA
Kim, Jinwoo, et al. “Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs.” IEEE Transactions on Components, Packaging & Manufacturing Technology, vol. 11, no. 12, Dec. 2021, pp. 2148–57. EBSCOhost, https://doi.org/10.1109/TCPMT.2021.3113664.
APA
Kim, J., Chekuri, V. C. K., Rahman, N. M., Dolatsara, M. A., Torun, H. M., Swaminathan, M., Mukhopadhyay, S., & Lim, S. K. (2021). Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs. IEEE Transactions on Components, Packaging & Manufacturing Technology, 11(12), 2148–2157. https://doi.org/10.1109/TCPMT.2021.3113664
Chicago
Kim, Jinwoo, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Majid Ahadi Dolatsara, Hakki Mert Torun, Madhavan Swaminathan, Saibal Mukhopadhyay, and Sung Kyu Lim. 2021. “Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs.” IEEE Transactions on Components, Packaging & Manufacturing Technology 11 (12): 2148–57. doi:10.1109/TCPMT.2021.3113664.