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A bipolar offset binary time-to-digital converter using time amplifiers based on time-to-current compensation.
- Source :
-
AEU: International Journal of Electronics & Communications . Feb2022, Vol. 144, pN.PAG-N.PAG. 1p. - Publication Year :
- 2022
-
Abstract
- A bipolar low-power pipeline time-to-digital converter (TDC) for digital phase-locked loop (DPLL) applications is implemented with six 1-bit cascaded stages. The stages consist of a compensated ×2 time amplifier (TA) using the time-to-current conversion technique, two modified SR-latch-based time comparators, and a static logic called offset-64, which aligns the output bit of the stage to create a 7-bit output code without the zero-gain issue. The presented mathematical analyses reveal the low sensitivity of the proposed TDC to the offset of the TA. The layout of the proposed TDC was designed in a 65 nm CMOS technology. Post-layout simulation results demonstrate a 1.7 ps time resolution and power consumption of 450 μW for a sampling frequency of 125 MS/s. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 14348411
- Volume :
- 144
- Database :
- Academic Search Index
- Journal :
- AEU: International Journal of Electronics & Communications
- Publication Type :
- Academic Journal
- Accession number :
- 154267461
- Full Text :
- https://doi.org/10.1016/j.aeue.2021.154072