A BiCMOS frontend electronics chipset for the readout of the INO-ICAL RPC detector.

This paper presents a BiCMOS voltage amplifier-based high-speed frontend electronics (FEE) chipset, designed in 0. 35 μ m SiGe BiCMOS technology. This chipset comprises two ASICs, namely a quad voltage amplifier ASIC and an octal comparator ASIC. The two-chip FEE is designed for the readout of large area, single-gap, avalanche mode Resistive Plate Chamber (RPC) detectors of the Iron Calorimeter (ICAL) experiment of the India based Neutrino Observatory (INO). The use of a voltage amplifier-based FEE topology along with a separate comparator ASIC resulted in a stable high gain and high-speed FEE operation in the presence of a large number of detector channels. This FEE solution has a total amplifier gain of 74, overall timing precision of 140 ps (RMS), and power consumption of 25 mW/channel. It exhibits pixel-wise detector efficiency larger than 90% along with position- and time-resolution of 1 cm RMS, and 1 ns RMS, respectively, when used with a prototype INO-ICAL RPC detector of size 1.85 m × 1.75 m. Furthermore, the performance of the FEE is not affected by the presence of the magnetic field (1.3 T) used in the experiment. [ABSTRACT FROM AUTHOR]