A write bit-line free sub-threshold SRAM cell with fully half-select free feature and high reliability for ultra-low power applications.

MLA

Karamimanesh, Mehrzad, et al. “A Write Bit-Line Free Sub-Threshold SRAM Cell with Fully Half-Select Free Feature and High Reliability for Ultra-Low Power Applications.” AEU: International Journal of Electronics & Communications, vol. 145, Feb. 2022, p. N.PAG. EBSCOhost, https://doi.org/10.1016/j.aeue.2021.154075.

APA

Karamimanesh, M., Abiri, E., Hassanli, K., Salehi, M. R., & Darabi, A. (2022). A write bit-line free sub-threshold SRAM cell with fully half-select free feature and high reliability for ultra-low power applications. AEU: International Journal of Electronics & Communications, 145, N.PAG. https://doi.org/10.1016/j.aeue.2021.154075

Chicago

Karamimanesh, Mehrzad, Ebrahim Abiri, Kourosh Hassanli, Mohammad Reza Salehi, and Abdolreza Darabi. 2022. “A Write Bit-Line Free Sub-Threshold SRAM Cell with Fully Half-Select Free Feature and High Reliability for Ultra-Low Power Applications.” AEU: International Journal of Electronics & Communications 145 (February): N.PAG. doi:10.1016/j.aeue.2021.154075.