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A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS.
- Source :
-
Circuits, Systems & Signal Processing . Mar2022, Vol. 41 Issue 3, p1299-1323. 25p. - Publication Year :
- 2022
-
Abstract
- In this work, a dual loop all-digital phase locked loop (ADPLL) is designed to obtain a fast locking, low power and low jitter for SoC and battery-operated applications. The high speed and high-resolution 4-bit flash time to digital converter (TDC) is also proposed to achieve low jitter and fast locking in ADPLL. The flash TDC uses a foreground calibration to make the ADPLL work robustly over PVT variations. In present work, fasting settling time of 1 μs and low power is achieved for proposed ADPLL owing to flash-based TDC and dual loop architecture. The proposed 4-bit flash TDC achieves a resolution of 6 ps. A low-phase noise voltage-controlled oscillator based on inverters is designed to obtain a reduced jitter in ADPLL. The ADPLL is implemented in a 180-nm SCL digital CMOS technology. The achieved phase noise of proposed ADPLL is − 128.2 dBc/Hz at an offset of 100 MHz. At an output frequency of 1.6 GHz, the periodic jitter of ADPLL is 7.8 ps, and power consumption is 6.5 mW. [ABSTRACT FROM AUTHOR]
- Subjects :
- *PHASE-locked loops
*VOLTAGE-controlled oscillators
*PHASE noise
Subjects
Details
- Language :
- English
- ISSN :
- 0278081X
- Volume :
- 41
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- Circuits, Systems & Signal Processing
- Publication Type :
- Academic Journal
- Accession number :
- 155260873
- Full Text :
- https://doi.org/10.1007/s00034-021-01861-z