Compensation of power quality problems through DSTATCOM using various phase locked loops.

The control algorithm of a DSTATCOM majorly influences its function. The key role of a phase locked loop (PLL) as a fundamental extractor in the control algorithm is inevitable. It is used to extract the information of the fundamental like phase angle, frequency and amplitude from the distorted voltage/current signal. According to the information collected, the performance of the control algorithm of the DSTATCOM is judged for various conditions like unbalanced and distorted harmonic condition. This paper presents the study of three PLLs, namely unified three-phase signal processor PLL (UTSP), multi-sequence harmonic decoupling PLL (MSHDC) and harmonic/inter-harmonic DC offset (HIHDO) PLL. An unconstrained optimization problem has been formulated with DC and AC bus voltage errors. The gains of proportional integral controller are projected using RAO algorithm. It is an algorithm specific type and parameter less. The DSTATCOM is able to compensate the reactive power and mitigate the grid current harmonics which are caused due to a nonlinear load through an optimized PI controller for the considered PLL the control algorithms. An analysis of performance using simulation results, dynamic response and complexity in computation has been made for the PLLs considered. The fast recovery during dynamic conditions of the system has opted HIHDO PLL as better one among the other two proposed PLLs. The laboratory performance of the considered system for HIHDO PLL using d-SPACE has been provided. [ABSTRACT FROM AUTHOR]