A Double Bit Approximate Adder Providing a New Design Perspective for Gate-Level Design.

In the modern Block-chain and Artificial Intelligence era, energy efficiency has become one of the most important design concerns. Approximate computing is a new and an evolving field promising to provide energy-accuracy trade-off. Several applications are tolerant to small degradation in results, and hence tasks like image and video processing are candidates to benefit from Approximate Computing. In this paper, we propose a new design approach for designing approximate adders and further optimize the accuracy and cost metrics. Our approach is based on minimizing the errors while cascading more than one 1-bit adder. We insert | error | = 1 on specific locations to achieve a reasonable circuit minimization and reduce the error × count gate cost. We compare our design with exact adder and relevant state-of-the-art approximate adders. Through analysis and simulations, we show that our approach provides higher accuracy and far better performance compared with other designs. The proposed double bit approximate adder provides more than 25% savings in gate count compared with the exact adder, has a mean absolute error of 0.25 which is lowest among all the reference approximate adders and reduces the power-delay product by more than 60% compared to the exact adder. When employed for image filtering, the proposed design provides a PSNR avg of 96%, a SNR avg of 95% and a SSIM avg of 91% relative to the actual results, while the second best approximate adder only achieves 64%, 54% and 71% of these image quality metrics, respectively. [ABSTRACT FROM AUTHOR]