Back to Search
Start Over
New dynamic logic style for energy efficient tag comparators.
- Source :
-
Microprocessors & Microsystems . Apr2022, Vol. 90, pN.PAG-N.PAG. 1p. - Publication Year :
- 2022
-
Abstract
- In this paper, a new dynamic logic style is proposed to reduce the power consumption and delay of wide fan-in gates used in tag comparators. In the proposed dynamic circuit, a large pull-down network (PDN) is partitioned into smaller networks to decrease the parasitic capacitance on the dynamic node. As a result, a weak keeper transistor is sufficient to achieve the desired robustness, and hence the contention current between the keeper transistor and pull-down networks is reduced. Lower contention causes lower delay and power consumption in the proposed dynamic circuit. Simulation of wide fan-in OR gates and 40-bit tag comparators are performed using HSPICE simulator in a 90 nm CMOS technology model. Simulation results indicate 38% and 42% reduction in power and delay, respectively, at the same noise immunity compared to the conventional dynamic circuit for 64-bit OR gates. In addition, simulation results exhibit 34% and 21% reduction in the power consumption and delay of the proposed tag comparator, respectively, compared to the conventional design at the same noise immunity. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 01419331
- Volume :
- 90
- Database :
- Academic Search Index
- Journal :
- Microprocessors & Microsystems
- Publication Type :
- Academic Journal
- Accession number :
- 156457552
- Full Text :
- https://doi.org/10.1016/j.micpro.2022.104522