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Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . May2022, Vol. 69 Issue 5, p1858-1870. 13p. - Publication Year :
- 2022
-
Abstract
- This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115 $\mu \text{s}$ , overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL. [ABSTRACT FROM AUTHOR]
- Subjects :
- *PHASE noise
*FREQUENCY synthesizers
*PHASE-locked loops
*PHASE detectors
Subjects
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 69
- Issue :
- 5
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 156630291
- Full Text :
- https://doi.org/10.1109/TCSI.2022.3146788