Cite
A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling.
MLA
“A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 69, no. 5, May 2022, pp. 2203–11. EBSCOhost, https://doi.org/10.1109/TCSI.2022.3150583.
APA
A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling. (2022). IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 69(5), 2203–2211. https://doi.org/10.1109/TCSI.2022.3150583
Chicago
“A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling.” 2022. IEEE Transactions on Circuits & Systems. Part I: Regular Papers 69 (5): 2203–11. doi:10.1109/TCSI.2022.3150583.