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Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks.
- Source :
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems . Jun2022, Vol. 41 Issue 6, p1716-1729. 14p. - Publication Year :
- 2022
-
Abstract
- Logic locking has emerged as a prominent key-driven technique to protect the integrity of integrated circuits. However, novel machine-learning-based attacks have recently been introduced to challenge the security foundations of locking schemes. These attacks are able to recover a significant percentage of the key without having access to an activated circuit. This article address this issue through two focal points. First, we present a theoretical model to test locking schemes for key-related structural leakage that can be exploited by machine learning. Second, based on the theoretical model, we introduce D-MUX: a deceptive multiplexer-based logic-locking scheme that is resilient against structure-exploiting machine learning attacks. Through the design of D-MUX, we uncover a major fallacy in the existing multiplexer-based locking schemes in the form of a structural-analysis attack. Finally, an extensive cost evaluation of D-MUX is presented. To the best of our knowledge, D-MUX is the first machine-learning-resilient locking scheme capable of protecting against all known learning-based attacks. Hereby, the presented work offers a starting point for the design and evaluation of future-generation logic locking in the era of machine learning. [ABSTRACT FROM AUTHOR]
- Subjects :
- *INTEGRATED circuits
*LOGIC
*MACHINE learning
*HARDWARE
*LOGIC circuits
Subjects
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 41
- Issue :
- 6
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 157007947
- Full Text :
- https://doi.org/10.1109/TCAD.2021.3100275