Cite
Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic.
MLA
Wang, Xiao-Yuan, et al. “Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 69, no. 6, June 2022, pp. 2423–34. EBSCOhost, https://doi.org/10.1109/TCSI.2022.3151920.
APA
Wang, X.-Y., Dong, C.-T., Zhou, P.-F., Nandi, S. K., Nath, S. K., Elliman, R. G., Iu, H. H.-C., Kang, S.-M., & Eshraghian, J. K. (2022). Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 69(6), 2423–2434. https://doi.org/10.1109/TCSI.2022.3151920
Chicago
Wang, Xiao-Yuan, Chuan-Tao Dong, Peng-Fei Zhou, Sanjoy Kumar Nandi, Shimul Kanti Nath, Robert G. Elliman, Herbert Ho-Ching Iu, Sung-Mo Kang, and Jason K. Eshraghian. 2022. “Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 69 (6): 2423–34. doi:10.1109/TCSI.2022.3151920.