SE Performance of D-FF Designs With Different V T Options at Near-Threshold Supply Voltages in 7-nm Bulk FinFET Technology.

Power consumption for integrated circuits (ICs) fabricated at advanced technology nodes is a primary concern for application-specific IC (ASIC) designers. To reduce power consumption, designers use transistors with different threshold voltage ($V_{\mathrm {T}}$) options and may reduce the supply voltage, oftentimes to as low as transistor-threshold-voltage levels. This work investigates the effects of these two popular techniques, different $V_{\mathrm {T}}$ options, and near-threshold-voltage (NTV) operation on the single-event (SE) performance of conventional D flip-flop (D-FF) cells in low-power applications. Results indicate that at near NTV levels, the SE cross section increases by two orders of magnitude, and the low $V_{\mathrm {T}}$ (LVT) option yields the best SE performance in comparison to the standard $V_{\mathrm {T}}$ (SVT) and ultralow $V_{\mathrm {T}}$ (uLVT) options. [ABSTRACT FROM AUTHOR]