Efficient hardware design of a deep U-net model for pixel-level ECG classification in healthcare device.

Nowadays, deep learning algorithm has been widely used for automatic electrocardiogram (ECG) classification. However, most algorithms can only classify single heartbeat, which requires complex heartbeat extraction preprocessing. In addition, the traditional software implementation on CPU or GPU platform faces the challenge of low computing efficiency and high resource consumption. In this work, a deep one-dimensional (1D) U-net is proposed, which can classify the original continuous ECG segment at the pixel level. And an efficient hardware architecture is presented to implement the 1D U-net. A two-stage pipeline Winograd structure is designed to increase computing efficiency. A 3D processing element (PE) array is developed to improve resource utilization and overall throughput. Implemented on Xilinx Zynq ZC706 board, experimental results show that the proposed 1D U-net achieves an average accuracy of 95.55% for the pixel-level classification of five heartbeats. In terms of hardware performance, resource efficiency and computing efficiency reach 8.27 GOPS/kLUT and 123% respectively at 200 MHz clock frequency. [ABSTRACT FROM AUTHOR]