Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight.

While considering the low power demand as a fundamental bottleneck for nanoscale devices, this work comprehensively investigates a novel concept that incorporates the area-scaled tunneling in a nanosheet field-effect transistor (NSFET) at a 5-nm technology node. Integrating the area scale tunneling phenomenon with NSFET provides improved electrical performance. We observed ${\sim } 50\times $ improvement in drain current and $\sim 2\times $ improvement in subthreshold slope (SS) by incorporating epitaxial layer over the source region underneath the gate. Furthermore, 100 mV of the shift in tunneling onset voltage (${V}_{T, \mathrm{\scriptscriptstyle ON}}$) is also noted when source doping increases from $1 \times 10^{{18}}$ to $1 \times 10^{{20}}$ cm $^{-{3}}$. The gate–source overlap (${L}_{\text {OV}}$) significantly improves the transconductance without sacrificing the output resistance. It is examined that epitaxial layer thickness (${T}_{\text {EPI}}$) of 3–4 nm gives the best possible drive current for the proposed device. However, the OFF current exhibits an inversely proportional relation with ${T}_{\text {EPI}}$. It is worth highlighting that optimum ${T}_{\text {EPI}}$ can be determined by only considering the suitable epitaxial layer doping profile (${N}_{\text {EPI}}$). A linear shift in ${V}_{T, \mathrm{\scriptscriptstyle ON}}$ of the proposed device with work function (WF) is also reported in our work. Finally, the concept of multiple stacking is explored to boost the device’s performance. Including the presented device design guidelines, the ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ ratio of $\sim 4.5 \times 10^{{8}}$ with an average SS of ~20 mV/dec is successfully demonstrated for the proposed device. [ABSTRACT FROM AUTHOR]