Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures.

MLA

Janwadkar, Sudhanshu, and Rasika Dhavse. “Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures.” Journal of Circuits, Systems & Computers, vol. 31, no. 13, Sept. 2022, pp. 1–34. EBSCOhost, https://doi.org/10.1142/S0218126622502395.

APA

Janwadkar, S., & Dhavse, R. (2022). Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures. Journal of Circuits, Systems & Computers, 31(13), 1–34. https://doi.org/10.1142/S0218126622502395

Chicago

Janwadkar, Sudhanshu, and Rasika Dhavse. 2022. “Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures.” Journal of Circuits, Systems & Computers 31 (13): 1–34. doi:10.1142/S0218126622502395.