Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p + /i/n + Silicon Nanowire.

MLA

Jang, Sung Hwan, and Tae Whan Kim. “Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p + /i/n + Silicon Nanowire.” IEEE Transactions on Electron Devices, vol. 69, no. 9, Sept. 2022, pp. 4909–13. EBSCOhost, https://doi.org/10.1109/TED.2022.3193349.

APA

Jang, S. H., & Kim, T. W. (2022). Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p + /i/n + Silicon Nanowire. IEEE Transactions on Electron Devices, 69(9), 4909–4913. https://doi.org/10.1109/TED.2022.3193349

Chicago

Jang, Sung Hwan, and Tae Whan Kim. 2022. “Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p + /i/n + Silicon Nanowire.” IEEE Transactions on Electron Devices 69 (9): 4909–13. doi:10.1109/TED.2022.3193349.