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An energy efficient symmetrical DAC switching scheme for single-ended SAR ADCs with zero reset energy and a 3-stage common-mode insensitive regenerative comparator.
- Source :
-
AEU: International Journal of Electronics & Communications . Dec2022, Vol. 157, pN.PAG-N.PAG. 1p. - Publication Year :
- 2022
-
Abstract
- A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme suitable for single-ended successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this paper. The proposed scheme synthesizes two reference voltages V r e f and V q to generate relevant voltage levels. The reference voltage V q is a quarter of the V r e f. To ease logic design, the V r e f is only utilized during the third phase of conversion with the MSB capacitor of each DAC. The proposed scheme reduces DAC's average switching energy and the area by 94.44 % and 50 % in comparison with the conventional single-ended scheme. Furthermore, a novel 3-stage common-mode insensitive regenerative comparator is proposed to reduce non-linearity errors caused by common-mode voltage variations of DAC. The proposed single-ended ADC is simulated in a standard 65-nm CMOS technology with a resolution of 8-bit and sampling rate of 25 MS/s. The simulation results corroborate that the ADC consumes 124 µW power with 1.2 V supply voltage and attain a 7.23 effective number of bits, resulting in a 33fJ/conversion step FOM. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 14348411
- Volume :
- 157
- Database :
- Academic Search Index
- Journal :
- AEU: International Journal of Electronics & Communications
- Publication Type :
- Academic Journal
- Accession number :
- 159953690
- Full Text :
- https://doi.org/10.1016/j.aeue.2022.154421