Forked-contact and dynamically-doped nanosheets to enhance Si and 2D-material devices at the limit of scaling.

• A novel Forked-Contact, Dynamically-Doped Multigate Nanosheet transistor that enables sub-30-nm pitch scaling is proposed. • DFT-NEGF fundamentals and cell layout extrinsics demonstrate a 10 nm scaling boost both for Si and 2D material devices. • The material-specific fundamental gate-length limit for transistor scaling for Si and 2D materials is also assessed here. We propose a novel Forked-Contact, Dynamically-Doped Multigate transistor as ultimate scaling booster for both Si and 2D materials in aggressively-scaled nanosheet devices. Using accurate dissipative DFT-NEGF atomistic-simulation fundamentals and cell layout extrinsics, we demonstrate superior and optimal device characteristics and invertor energy – delays down to sub-30-nm pitches, i.e., a 10 nm scaling boost compared to the nanosheet MOSFET references, regardless of the material system used. This gain is linked to a more compact architecture but does not change the material-specific fundamental gate-length limit that we also assess here. By switching from Si to 2D materials, however, an additional 5 nm reduction in gate length scaling could be enabled. [ABSTRACT FROM AUTHOR]