Cite
VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators.
MLA
Jing, Zhaokun, et al. “VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 69, no. 10, Oct. 2022, pp. 4028–41. EBSCOhost, https://doi.org/10.1109/TCSI.2022.3186024.
APA
Jing, Z., Yan, B., Yang, Y., & Huang, R. (2022). VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 69(10), 4028–4041. https://doi.org/10.1109/TCSI.2022.3186024
Chicago
Jing, Zhaokun, Bonan Yan, Yuchao Yang, and Ru Huang. 2022. “VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 69 (10): 4028–41. doi:10.1109/TCSI.2022.3186024.