Correction to “Leveraging Negative Capacitance CNTFETs for Image Processing: An Ultra-Efficient Ternary Image Edge Detection Hardware”.

In the above article , Fig. 5(b) belonged to another circuit (the Fe-CNTFET-based 2-transistor Schmitt trigger binary inverter, which is similar in the schematic to the circuit shown in Fig. 5 (a) of the above artice but with different flat band voltages), which was inserted in the revised version of the article by an unintentional mistake. The load line analysis of the circuit shown in Fig. 5 (a) of the article is shown in. For more clarity, the load line analysis has been plotted with more detail for Vin = 0.3V to 0.5V to indicate the performance of the ternary inverter in logic “1,” which matches the related VTC curve (Fig. 5 (c) shown in reference). [ABSTRACT FROM AUTHOR]