One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications.

This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms. [ABSTRACT FROM AUTHOR]