FPGA-Based Low-Cost Architecture for R-Peak Detection and Heart-Rate Calculation Using Lifting-Based Discrete Wavelet Transform.

This paper focuses on designing a field-programmable gate array (FPGA)-based architecture for R-peak detection and heart rate calculation using lifting-based discrete wavelet transform (DWT). An efficient and low-cost architecture for Daubechies 4 lifting-based DWT for a decomposition level of four is also proposed. The proposed architecture is folded after the first decomposition level to avoid repetitive blocks for different decomposition levels. The noise-removal and preprocessing of the electrocardiogram (ECG) signals are carried out using lifting-based DWT. The 16-bit fixed-point representation is employed throughout the design to reduce the hardware complexity. The entire design is evaluated in both MATLAB R2020a and XILINX VIVADO 2017.4. The proposed architecture is validated using three ECG databases, namely the MIT-BIH arrhythmia, the MIT-BIH supraventricular, and the QT database. A total of 122 distinct ECG datasets are tested on FPGA to determine the effectiveness of the proposed R-peak detection architecture. The R-peaks detected using the proposed technique show no noticeable error with respect to actual R-peaks. The FPGA implementation is performed using the Artix-7 board that utilizes 2197 LUTs and 486 flip-flops at an operating frequency of 44 MHz. The proposed architecture achieves sensitivity, accuracy, positive predictivity, and detection rate of 99.52, 99.43, 99.91, and 0.565%, respectively, in MATLAB, and 99.44, 98.88, 99.43, and 1.09%, respectively, in FPGA. In terms of both hardware utilization and R-peak detection rate achieved, the proposed architecture is suitable to use as a part of low-cost smart biomedical devices to perform continuous monitoring of ECG signals and automatic detection of heart rates. [ABSTRACT FROM AUTHOR]