Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture.

Approximate Computing techniques are finding a central role in modern applications, by optimizing architectures to relax some computation but with a constrained inaccuracy. In many applications, the FFT algorithm is invariably applied and there is a need for approximate low energy hardware solutions to the FFT. The paper thus proposes an approximate, fixed-point, in-place, shared memory architecture for FFT. It is well observed that the energy at FFT I/Os is not strictly contiguous, hence the proposed FFT exploits this window to tune the error. The proposed FFT and its associated butterfly unit is constructed to efficiently incorporate approximate Toom–Cook multiplication. As said, a supporting function in error correction based on the sparsity patterns, is a feature of this design. The design synthesized at 32 n m shows on average, a 48.6% and 52.8% improvement in consumption of area and energy, respectively, with as less error as 0.1% with pruning. • Approximate Computing can exploit error resilience of the applications to reduce chip resources. • FFT is a fundamental block on chip and approximating FFT can accelerate many applications. • The proposed FFT is based on approximate Toom-Cook multiplication that has a reduced number of sub-multiplications. • Pre-computing the evaluations in Toom-Cook multiplication of the twiddle factors in the butterfly provides additional savings. • This design allows a secondary mode of operation in FFT to trade-off sparsity in the FFT outputs with the error in the final FFT sequence. [ABSTRACT FROM AUTHOR]