BonnLogic: Delay optimization by And-Or Path restructuring.

We present BonnLogic , a timing optimization framework that replaces critical paths by logically equivalent realizations with less delay. Our tool allows to revise early decisions on the logical structure of the netlist in late physical design. The core routine of our framework is a new algorithm that constructs delay-optimized circuits for alternating And - Or paths with prescribed input arrival times. It is a sophisticated dynamic programming algorithm which is a common generalization of the previously best approaches. In contrast to all earlier methods, we avoid fixing the structure of sub-solutions before deciding on how to combine them, significantly expanding the search space of the algorithm. Our algorithm provably fulfills the best known approximation guarantees, almost always computes delay-optimum solutions, and empirically outperforms all previous approaches. In addition, we show how any algorithm for And - Or paths optimization which is restricted to integral arrival times can be generalized to fractional arrival times with the same guarantees on the delay. The reduction to And - Or path optimization allows us to optimize general combinatorial paths of arbitrary length in our logic restructuring framework BonnLogic. The framework is applied successfully as a late step in an industrial physical design flow. Experiments demonstrate the effectiveness of BonnLogic on industrial 7 nm instances. • We describe a new dynamic program for delay optimization of extended And - Or Paths. • We extend any And - Or paths optimization from integral to fractional arrival times. • On more than 95% of our test instances, our algorithm finds a delay-optimum circuit. • We propose BonnLogic , a framework for timing optimization of logic paths. • Experiments on recent 7nm chips show the effectiveness of BonnLogic. [ABSTRACT FROM AUTHOR]