Area-efficient radiation-hardened 6 T SOI SRAM cell design using TDBC Transistors.

Single event upset (SEU) is a critical issue for the static random access memory (SRAM) exposed to irradiated environments. In this paper, an area-efficient 6 T SRAM cell design based on partially depleted silicon-on-insulator (PDSOI) technology is proposed to improve the ability to resist SEU using tunnel-diode body-contact (TDBC) transistors. The proposed cell and 6 T floating body (FB) SOI SRAM cell are fabricated using 130 nm PDSOI technology for comparison purposes. Pulsed laser experiments show that, at the nominal supply voltage of 1.2 V, the energy threshold of the proposed cell increases by 25.2 % compared to the 6 T FB SOI cell with a similar area. The energy threshold of the traditional T-gate body-contact (TB) cell is also compared with that of the proposed cell. • An area-efficient 6 T SRAM cell design based on PDSOI technology is proposed to improve the ability of resisting SEU. • The proposed cell and 6 T floating body SOI SRAM cell are fabricated using 130 nm PDSOI technology for comparison purposes. • The energy threshold of the proposed cell increases by 25.2 % compared to the 6 T FB SOI cell with a similar area. [ABSTRACT FROM AUTHOR]