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A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications.
- Source :
-
Microelectronics Journal . May2023, Vol. 135, pN.PAG-N.PAG. 1p. - Publication Year :
- 2023
-
Abstract
- A Digital-to-Time Converter based (DTC-based) fractional- N digital phase-locked loop (DPLL) using probability-density-shaping (PDS) spur immunity and quantization phase (Q-noise) reduction techniques is presented. PDS-DSM is used to generate a loop spur immunity control code for DTC. A diff type dither is proposed to further suppress the fractional spur. The loop nonlinearity will not cause fractional spurs if certain conditions are obeyed. Moreover, to reduce the quantization noise, a configurable Phase Interpolator (PI) with 0.125/0.25/0.5/1.0 division step is integrated with a multi-module divider (MMDIV), leading to an 18-dB Q-noise suppression. A reference doubler with duty-cycle correction is adopted to further reduce phase noise. The fractional spurs are greatly mitigated by combining the PDS-DSM and phase interpolator. A DPLL prototype using the aforementioned techniques was designed in a 40-nm standard CMOS process, occupying a 0.99 mm2 silicon area. At a near-integer- N frequency, i.e., near 2.23 GHz, with PDS turned on and off, the post-layout simulated fractional spur is −59 dBc and −20 dBc, respectively. The RMS jitter of the whole chip is 4.218 ps, corresponding to a figure of merit (FOM) of −220.5 dB. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00262692
- Volume :
- 135
- Database :
- Academic Search Index
- Journal :
- Microelectronics Journal
- Publication Type :
- Academic Journal
- Accession number :
- 162978662
- Full Text :
- https://doi.org/10.1016/j.mejo.2023.105753