Investigating the correlation between interface and dielectric trap densities in aged p-MOSFETs using current-voltage, charge pumping, and 1/f noise characterization techniques.

Dielectric defects play a crucial role in the reliability of MOSFETs. In this study, we aim to gain a deeper understanding of dielectrics' degradation by correlating the effective interface (N 2 D) and bulk (N B T) trap densities extracted by different characterization techniques (I-V, charge pumping, and 1/f noise) under different electrical stress conditions. Additionally, we establish an empirical relation between the increase of N B T (estimated via 1/f noise measurements) and N 2 D , e f f (estimated through the monitoring of threshold voltage shift) after stress. This relation is useful to calculate the expected increase in 1/f noise from the V T degradation models typically made available by the foundries to circuit designers. • Comparison of electrical techniques to extract trap densities under diverse stress conditions. • 1/f noise increases with stress only in the carrier number fluctuation regime (i.e., at low gate voltage overdrives). • We derive an empirical relationship between the stress-induced increase of 1/f noise and threshold voltage shift. [ABSTRACT FROM AUTHOR]