Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection.

Hardware Trojan (HT) is a severe security threat during the development of an integrated circuit that can deviate the IC from its normal function and/or leak sensitive information during in-field operations. Trojans are often inserted during the fabrication phase, and to have Trojan-free ICs; it is highly desirable to detect them during post-silicon testing. Different test pattern generation-based HT detection techniques are reported in the literature to detect the Trojan during post-silicon testing. The existing methods provide low coverage and require a large number of test patterns. This paper proposes a new test pattern generation-based HT detection technique that provides high coverage while requiring less number of patterns. The proposed technique generates the optimal number of test patterns that activate the rare events by framing the problem as multi-objective optimization and solving it through a non-dominated sorting genetic algorithm (NSGA-II). The Trojans are mostly inserted using rare-triggered nodes (highly vulnerable, low controllable, and low observable). Thus, our technique applies the generated patterns during post-silicon testing to activate Trojans. Further, we also present the use of checker (detection) logic along with a proposed approach to effectively detect the Trojan during testing. The experimental evaluation on ISCAS benchmarks shows that the proposed technique provides 12 times higher trigger coverage with 1/3 fewer test patterns than the best-known existing genetic algorithm-based technique. [ABSTRACT FROM AUTHOR]