Back to Search
Start Over
A 3–5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ADCs with a sampling rate of 4 GS/s.
- Source :
-
Microelectronics Journal . Sep2023, Vol. 139, pN.PAG-N.PAG. 1p. - Publication Year :
- 2023
-
Abstract
- This paper presents a high-speed, low-jitter, and high-precision clock receiver circuit (CLKRX) for time-interleaved ADCs with a sampling rate of 4 GS/s operating in the 3–5 GHz frequency range. The CLKRX circuit is composed of a continuous-time linear equalizer (CTLE) and a duty-cycle corrector (DCC). The CTLE featuring active feedback, negative Miller capacitance, and source-follower feedback is capable of enhancing the bandwidth, and improving the quality of the high-speed clock. Whereas the 3–5 GHz DCC module contains a common-mode voltage correction circuit and a wideband amplifier that corrects the input signal's duty cycle ranging from 20% to 80%. A second-order duty-cycle detection circuit is used in the feedback loop, which significantly improves the range and accuracy of duty-cycle correction and greatly reduces duty cycle jitter.The clock receiver circuit proposed in this paper was verified in a 28 nm CMOS process, and the test results show that the output duty cycle is corrected to 50 ± 0.1% within the input duty cycle range of 20–80% (3–5 GHz). [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00262692
- Volume :
- 139
- Database :
- Academic Search Index
- Journal :
- Microelectronics Journal
- Publication Type :
- Academic Journal
- Accession number :
- 170722115
- Full Text :
- https://doi.org/10.1016/j.mejo.2023.105889