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A dynamic power-efficient 4 GS/s CMOS comparator.
- Source :
-
AEU: International Journal of Electronics & Communications . Oct2023, Vol. 170, pN.PAG-N.PAG. 1p. - Publication Year :
- 2023
-
Abstract
- This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 14348411
- Volume :
- 170
- Database :
- Academic Search Index
- Journal :
- AEU: International Journal of Electronics & Communications
- Publication Type :
- Academic Journal
- Accession number :
- 171585844
- Full Text :
- https://doi.org/10.1016/j.aeue.2023.154812