Improved design and optimization of a 4-bit absolute-value detector.

This paper seeks to maximize results by reducing both consumption and propagation delays. The project then tackled the challenge of creating a 4-bit absolute value detector with static CMOS logic and pass transistor logic (PTL) to evaluate the two input values in 2's complement format in a novel way. This paper began by deriving the logical equation from the truth table of an absolute value detector and comparator when creating the project design. This paper then converts the equation into NAND, NOR gates and inverters to simplify the process of computing gate efforts, while also optimizing the topology to reduce the number of transistors and the amount of delay. Subsequently, this article determines the most advantageous gate efforts and total capacitance in order to evaluate the delay and energy expenditure. This paper seeks to balance delay and energy consumption by finding the optimal VDD which is 1.5 times the minimum delay. This paper, in turn, introduced the 4-bit absolute value comparator which decrease the power and delay. The time gap have is 20.586 seconds, which is less than the size-limited condition. This document calculates the ideal VDD value while allowing 1.5 times the minimal delay to achieve a balance between delay and energy efficiency. Consequently, this paper developed the 4-bit absolute value comparator. The delay time is no less than 20.586 seconds when the sizing is taken into consideration. [ABSTRACT FROM AUTHOR]