Design of 4-bit absolute-value detector with trade-off between propagation delay and energy consumption.

Modern electronic devices consider factors such as power consumption and propagation delay in order to attain best outcome. In response, this paper addresses an innovative design of 4-bit absolute value detector with CMOS and pass-transistor logic (PTL) to evaluate the two input values in 2's complement format. In addition, the design applies transistor sizing and voltage scaling techniques to maximize the circuit's efficiency and reduce its power consumption, in order to realize optimization goals of higher power-efficiency and more energy saving. The logical equations are first derived from the minterms of the truth table of absolute value detector and comparator. To facilitate the calculation, the optimum gate efforts and the total capacitance are figured out to calculate the critical path delay and the whole circuit's energy consumption. The optimum VDD is derived with the compromise of 1.5 times the minimum delay to handle the trade-off between the delay and total energy consumption. As a result, this design greatly optimizes the performance of absolute value circuit, which guarantees its great potential in electronics industry. [ABSTRACT FROM AUTHOR]