A 10-Gbps CTLE design using split-length input pair MOS Transistors.

MLA

Shehata, Ahmed, et al. “A 10-Gbps CTLE Design Using Split-Length Input Pair MOS Transistors.” International Journal of Electronics Letters, vol. 11, no. 4, Dec. 2023, pp. 449–58. EBSCOhost, https://doi.org/10.1080/21681724.2022.2117850.

APA

Shehata, A., Fahmy, G. A., & Ragai, H. F. (2023). A 10-Gbps CTLE design using split-length input pair MOS Transistors. International Journal of Electronics Letters, 11(4), 449–458. https://doi.org/10.1080/21681724.2022.2117850

Chicago

Shehata, Ahmed, Ghazal A. Fahmy, and Hany F. Ragai. 2023. “A 10-Gbps CTLE Design Using Split-Length Input Pair MOS Transistors.” International Journal of Electronics Letters 11 (4): 449–58. doi:10.1080/21681724.2022.2117850.