Process engineers passing the buck to designers over low-k.

The article reports that papers and panels at the recent International Interconnect Technology Conference here showed growing fissures in the once-solid compact between the back-end-of-line (BEOL) process engineers who create the interconnect stacks in ICs and the chip designers who use them. In the past, as interconnect geometries have shrunk, process engineers have selected new materials and invented techniques to ensure chip designers would have viable metal resistance and inter metal capacitance with which to do their work. But beginning at the 65-nanometer node, BEOL engineers are retreating as the interconnect integration task goes from hard to Herculean.