Exploration and analysis of n-FinFET implementing stacked high-K at 08 nm gate length.

FinFETs ensured the continuation of semiconductor industry with reliable, high performance and low power devices fabricated at sub-100 nm technology nodes. These FinFETs are able to suppress the Short Channel Effects quite effectively while decreasing the leakage currents. Below 22 nm gate lengths, the SCEs resurfaced. To suppress these effects, the thickness of the gate oxide reduced. As the gate oxide thickness reached below 2 nm, the leakage currents started increasing again. Thus arose the need for replacing SiO2 with high permittivity dielectric materials like Zirconium Dioxide, Hafnium Oxide, Aluminum Oxide and Silicon Nitrate. Research also suggested the use of Multi Fin architectures to enhance the drain currents. The focus of this paper is to develop multiple fin 08 nm gate length SOI FinFETs having three fin architecture where the gate oxide of each fin consists of a stacked combination of 0.5 nm of high-k dielectrics atop another layer of 0.5 nm of SiO2 to reduce the leakage currents and other SCEs. The use of 3-Fin structures significantly enhances the drain current leading to higher switching speeds for faster CMOS fabrication and optimized device performance towards semiconductor industry. [ABSTRACT FROM AUTHOR]